As a part of the verification team, ASIC/SoC Verification engineers are responsible for implementing the verification models, integrating the verification environments, develop script based utilities and support verification activities.
Essential Technical Experience Must be familiar with ASIC/SoC verification methodologies and levels – functional, RTL, gate level, timing, etc., BIST and processor verification.
Must have good understanding about BFM and TLM Must have hands-on experience in Verilog/system Verilog/VHDL and C/C++ or SystemC.
Hands on experience of the design verification methodologies such as VMM/OVM/UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation.
Must have experience in Make and scripting using perl, Tcl, etc. Must have exposure to functional coverage and bug management schemes.
Self motivation, flexibility, with strong inter-personal skills.
Good communication skills, oral and written.